How Many Registers Finite State Machine

A finite-state machine (FSM) is a mechanism whose output is dependent not only on the current state of the input, merely too on past input and output values.

Whenever you lot need to create some sort of fourth dimension-dependent algorithm in VHDL, or if yous are faced with the problem of implementing a computer plan in an FPGA, it can usually be solved by using an FSM.

State-machines in VHDL are clocked processes whose outputs are controlled by the value of a state signal. The state indicate serves as an internal retentivity of what happened in the previous iteration.

This weblog post is part of the Bones VHDL Tutorials series.

Consider the states of the traffic lights at this intersection:

The traffic lights have a finite number of states, which we have given identifiable names. Our example state machine has no decision-making inputs, the output is the state of the lights in n/due south and west/east directions. It is elapsed time and the previous state of outputs which advances this country auto.

We tin represent states in VHDL using an enumerated type. These are data types only like signed or unsigned, but instead of integer numbers, we can supply a custom list of possible values. In fact, if you accept a await in the std_logic_1164 bundle, you will detect that the std_ulogic blazon is nothing more an enumerated type with the values 'U', 'X', '0', '1', 'Z', 'W', '50', 'H', and '-' listed as enumeration values.

Once we take our enumerated blazon, we tin can declare a bespeak of the new type which tin be used for keeping runway of the FSM'due south current state.

The syntax for declaring a signal with an enumerated type in VHDL is:
type <type_name> is (<state_name1>, <state_name2>, ...); signal <signal_name> : <type_name>;

Using the land signal, the finite-land machine can and then be implemented in a process with a Example statement. The Case statement contains a When statement for each of the possible states, causing the program to take dissimilar paths for every country. The When statement can also incorporate code which should be executed while in that particular state. The state will then typically change when a predefined condition is met.

This is a template for 1-process state machine:
process(Clk) is brainstorm if rising_edge(Clk) and then if nRst = '0' then State <= <reset_state>; else case Country is when <state_name> => <set_outputs_for_this_state_here> if <state_change_condition_is_true> then State <= <next_state_name>; cease if; ... finish case; stop if; cease if; stop process;

Note:
There are several ways to create an FSM in VHDL. Read about the unlike styles here:
1-process vs two-process vs 3-procedure country auto

Exercise

In this video tutorial we will learn how to create a finite-state car in VHDL:

The final code for the state machine testbench:

library ieee; utilize ieee.std_logic_1164.all; use ieee.numeric_std.all;  entity T20_FiniteStateMachineTb is end entity;  architecture sim of T20_FiniteStateMachineTb is      -- Nosotros are using a depression clock frequency to speed upwards the simulation     constant ClockFrequencyHz : integer := 100; -- 100 Hz     constant ClockPeriod : time := 1000 ms / ClockFrequencyHz;      signal Clk         : std_logic := 'i';     signal nRst        : std_logic := '0';     signal NorthRed    : std_logic;     signal NorthYellow : std_logic;     betoken NorthGreen  : std_logic;     signal WestRed     : std_logic;     signal WestYellow  : std_logic;     signal WestGreen   : std_logic;  begin      -- The Device Under Test (DUT)     i_TrafficLights : entity work.T20_TrafficLights(rtl)     generic map(ClockFrequencyHz => ClockFrequencyHz)     port map (         Clk         => Clk,         nRst        => nRst,         NorthRed    => NorthRed,         NorthYellow => NorthYellow,         NorthGreen  => NorthGreen,         WestRed     => WestRed,         WestYellow  => WestYellow,         WestGreen   => WestGreen);      -- Process for generating clock     Clk <= not Clk subsequently ClockPeriod / 2;      -- Testbench sequence     process is     begin         look until rising_edge(Clk);         expect until rising_edge(Clk);          -- Accept the DUT out of reset         nRst <= '1';          wait;     end process;  end architecture;

The final lawmaking for the state machine module:

library ieee; employ ieee.std_logic_1164.all; use ieee.numeric_std.all;  entity T20_TrafficLights is generic(ClockFrequencyHz : integer); port(     Clk         : in std_logic;     nRst        : in std_logic; -- Negative reset     NorthRed    : out std_logic;     NorthYellow : out std_logic;     NorthGreen  : out std_logic;     WestRed     : out std_logic;     WestYellow  : out std_logic;     WestGreen   : out std_logic); end entity;  architecture rtl of T20_TrafficLights is      -- Enumerated blazon proclamation and state bespeak declaration     type t_State is (NorthNext, StartNorth, North, StopNorth,                         WestNext, StartWest, Due west, StopWest);     point State : t_State;      -- Counter for counting clock periods, one minute max     signal Counter : integer range 0 to ClockFrequencyHz * 60;  begin      procedure(Clk) is     begin         if rising_edge(Clk) and then             if nRst = '0' then                 -- Reset values                 State   <= NorthNext;                 Counter <= 0;                 NorthRed    <= '1';                 NorthYellow <= '0';                 NorthGreen  <= '0';                 WestRed     <= 'ane';                 WestYellow  <= '0';                 WestGreen   <= '0';              else                 -- Default values                 NorthRed    <= '0';                 NorthYellow <= '0';                 NorthGreen  <= '0';                 WestRed     <= '0';                 WestYellow  <= '0';                 WestGreen   <= '0';                  Counter <= Counter + ane;                  instance State is                      -- Red in all directions                     when NorthNext =>                         NorthRed <= '1';                         WestRed  <= '1';                         -- If five seconds accept passed                         if Counter = ClockFrequencyHz * five -1 then                             Counter <= 0;                             State   <= StartNorth;                         finish if;                      -- Blood-red and yellow in north/southward direction                     when StartNorth =>                         NorthRed    <= 'i';                         NorthYellow <= '1';                         WestRed     <= '1';                         -- If 5 seconds take passed                         if Counter = ClockFrequencyHz * 5 -1 and then                             Counter <= 0;                             Land   <= North;                         cease if;                      -- Green in n/due south management                     when North =>                         NorthGreen <= '1';                         WestRed    <= '1';                         -- If 1 infinitesimal has passed                         if Counter = ClockFrequencyHz * threescore -1 then                             Counter <= 0;                             State   <= StopNorth;                         end if;                      -- Yellow in north/due south management                     when StopNorth =>                         NorthYellow <= '1';                         WestRed     <= 'i';                         -- If 5 seconds accept passed                         if Counter = ClockFrequencyHz * five -one then                             Counter <= 0;                             State   <= WestNext;                         terminate if;                      -- Reddish in all directions                     when WestNext =>                         NorthRed <= '1';                         WestRed  <= 'one';                         -- If five seconds take passed                         if Counter = ClockFrequencyHz * 5 -1 then                             Counter <= 0;                             State   <= StartWest;                         end if;                      -- Red and yellow in west/east direction                     when StartWest =>                         NorthRed   <= '1';                         WestRed    <= '1';                         WestYellow <= '1';                         -- If v seconds have passed                         if Counter = ClockFrequencyHz * 5 -1 then                             Counter <= 0;                             State   <= Westward;                         end if;                      -- Green in west/due east direction                     when Westward =>                         NorthRed  <= '1';                         WestGreen <= '1';                         -- If 1 infinitesimal has passed                         if Counter = ClockFrequencyHz * threescore -ane then                             Counter <= 0;                             State   <= StopWest;                         end if;                      -- Yellow in west/east direction                     when StopWest =>                         NorthRed   <= '1';                         WestYellow <= '1';                         -- If 5 seconds accept passed                         if Counter = ClockFrequencyHz * v -one and so                             Counter <= 0;                             Country   <= NorthNext;                         end if;                  stop instance;              end if;         terminate if;     terminate process;  terminate architecture;

The waveform subsequently we entered the run 5 min command in the ModelSim console:

Analysis

We declared an enumerated type with all the viii different states of our traffic lights. And so, we declared a land signal of this new type that nosotros created. This means that the signal tin only have ane of the eight named state values, and no other values.

The FSM was implemented using a Instance-argument inside a clocked process. On each rise edge of the clock, the process wakes upwards, and the land betoken is evaluated. The code within exactly one of the when choices (branches) is allowed to run, depending on the electric current state.

In our lawmaking, it is the value of the Counter indicate that triggers state changes. When the Counter reaches a predefined value, representing v seconds or i minute, a new state encoding is assigned to the Land signal. Then, when the procedure wakes upwardly on the next rise edge of the clock afterward the state value has been updated, the FSM is in a different land.

Annotation that we are not assigning '0' to any signal in any of the when choices. This is because we have given all the output signals a default value of '0' at the beginning of the process. You may remember from a previous tutorial that it is the terminal value which is assigned to a signal that becomes constructive. Signal assignments become effective only after the process terminates. If we assign '0' to the signal at the beginning of the process, and then 'ane' in one of the when choices, the signal volition get the value 'one'.

We can come across from the waveform that the State signal cycles through the 8 states. The steady green states concluding for ane minute, the waveform prototype has therefore been cut in the North and West states.

Takeaway

Algorithms are unremarkably implemented as finite-state machines (FSMs)
An FSM can be implemented by using a instance statement in a clocked process
FSM states can be implemented in an enumerated type

Become to the next tutorial »

I'1000 from Norway, only I alive in Bangkok, Thailand. Before I started VHDLwhiz, I worked as an FPGA engineer in the defense industry. I earned my master's degree in informatics at the University of Oslo.