Which Mips Registers Can Hold Iee 754 Single Precision

The MIPS Instruction-Ready Compages

[H&P �2.12] � The MIPS instruction set illustrates four underlying principles of hardware design:

one. Simplicity favors regularity.

2. Smaller is faster.

3. Expert design demands compromise.

four. Brand the mutual case fast.

The MIPS instruction-set compages has characteristics based on conclusions from previous lectures.

� � Information technology is a load-store architecture that uses general-purpose registers.

� � It has only two addressing modes, displacement and immediate, but can synthesize other of import modes from them.

� � It supports 8-, 16-, 32-, and 64-bit integers, and 32- and 64-bit IEEE 754 floating-point numbers.

� � It has an orthogonal set of instructions to manipulate these data types.

� � It has separate comparing and branching instructions.� (This is an example of making the common example fast.)

MIPS has xxx-ii 64-fleck general-purpose registers, named R0, R1, � , R31.

�� R0 always contains 0 (loading it with some other value has no effect). �

It has 32 floating-betoken registers, which can concord either single-precision (32-bit) or double-precision (64-bit) values.

This is an example of smaller is faster�using a unmarried register set would make register-accost fields larger and make accesses take longer.

Addressing modes

Displacement and immediate modes both have xvi-scrap fields.

How can nosotros synthesize other important addressing modes?

�� Register indirect: �

�� Direct: �

�� Scaled: �

�� Retentiveness indirect: �

Like the PowerPC, MIPS can select either Large Endian or Little Endian byte ordering.

Memory is byte addressable with a 64-flake address.

MIPS instruction formats

Simplicity favors regularity � so all MIPS arithmetics instructions have exactly three operands.

For example,

dadd�� r3, r1, r2�� Regs[r3] � Regs[r1] + Regs[r2]

dsub�� r3, r1, r2�� Regs[r3] � Regs[r1] � Regs[r2]

Skillful blueprint demands compromise � and so instructions are stock-still length (32 bits).� This requires different instruction formats.� This tabular array gives a summary of the three formats.

Format	6 bits	5 $.25	five bits	5 bits	five $.25	6 bits	Comments
R	op	rs	rt	rd	shamt	funct	�� Arithmetic
I	op	rs	rt	address/firsthand			Transfer, branch, firsthand
J	op	target address					Jump

Let�s have a look at each of these formats in more detail.

An R-type instruction has this format.

half-dozen	five	5	five	5	6
Opcode	rs	rt	rd	shamt	funct
ALU op	Operand one	Operand 2	Event	Shift amt.	add, sub, etc.

This format is used for both arithmetic and boolean operations.� In general, the shamt field is 0 for arithmetic operations, and the rs field is 0 for logical operations.

An I-type instruction has this format.

6	v	5	16
Opcode	rs	rt	Immediate
Load/Store	Source register	Destination register	Immediate [rt � rs op immediate]
Conditional branch	Comparand 1	Comparand 2	PC-relative first [if rs rel rt then branch]

A J-type teaching has this format.

6	26
Opcode	Kickoff
Jump [& link]	Target address_4..29
Jump register	Register to spring to	JR function code

MIPS instructions

Hither are a few MIPS instructions.� The text has another list, and a comprehensive list (for MIPS IV) can be establish at techpubs.sgi.com/library/manuals/2000/ 007-2597-001/pdf/007-2597-001.pdf

Arithmetic instructions

Instruction	Example	Meaning	Comments
Add together	add R1,R2,R3	R1 � R2+R3
Subtract	sub R1,R2,R3	R1 � R2�R3
Add immediate	addi R1,R2,10	R1 � R2+10	Adds a constant
Add unsigned	addu R1,R2,R3	R1 � R2+R3	No trap on o�flo.
Add immed uns�d	addiu R1,R2,10	R1 � R2+x

Logical instructions

Instruction	Example	Meaning	Comments
And	and R1,R2,R3	R1 � R2&R3
Or	or R1,R2,R3	R1 � R2\|R3
And immediate	andi R1,R2,x	R1 � R2&10	and with a abiding
Shift left logical	sll R1,R2,10	R1 � R2<<x	Shift left by constant
Shift right logical	srl R1,R2,10	R1 � R2>>10	Shift right past constant

Load/store

Instruction	Instance	Significant	Comments
Load word	lw R1,ten(R2)	R1 � Mem [R2+ten]	Memory to annals
Store give-and-take	sw R1,10(R2)	Mem[R2+10] � R1	Register to memory
Load upper immed.	lui R1,10	R1 � x � two¹⁶	Load constant into upper 16 bits of word

Conditional branch

Pedagogy	Instance	Meaning
Co-operative on equal	beq R1,R2,ten	if (R1==R2) goto PC+4+x
Branch on not equal	bne R1,R2,x	if (R1!=R2) goto PC+four+10
Set on less than	slt R1,R2,R3	if (R2<R3) R1 � ane; else R1=0

16-bit signed starting time is shifted left ii places and added to the program counter.� (The programme counter is pointing to the next sequential didactics.)

Unconditional leap

Instruction	Example	Meaning	Comments
Jump	j g	goto 1000	Spring to target address
Leap annals	jr R31	goto R31	For switch or procedure return
Spring and link	jal 1000	R31 � PC+4; goto 1000	For procedure call
Jump and link annals	jalr R1	R31 � PC+four; PC � R2	For procedure call

Floating-point

Instruction	Example	Meaning	Comments
Add double	add.d F1,F2,F3	F1 � F2+F3	64-bit operation
Subtract unmarried	sub.s F1,F2,F3	F1 � F2�F3	32-bit operation
Multiply paired single	mul.ps F1,F2,F3	F1 � F2 � F3	Two 32-bit operations simultaneously

Let�s have a look at how frequently these instructions are used.� Here are frequencies for five SPECint2000 programs.

Below are frequencies for five SPECfp2000 programs.

Compare these frequen�cies with the frequencies for integer programs.

Why are there more loads than stores?

What differences do you lot see in instruction frequencies?�

Sample MIPS program

# sumit.asm

# Unproblematic routine to sum Due north integers to demo a loop.

# Author: R.N. Ciminero

# Revision date: x-06-93 Original def.

# See Patterson & Hennessy pg. A-46 for system services.

�� .text

�� .globl principal

main:

�� li�� $v0,four�� # load code for print_string

�� la�� $a0, msg1�� # address of cord to print

�� syscall�� # print cord

�� li�� $v0,v�� # load code for read_int

�� syscall�� # input N

�� move� $t0,$v0�� # save

�� li�� $t1, 0�� # initialize counter (i)

�� li�� $t2, 0�� # initialize sum

loop: addi� $t1, $t1, 1�� # i = i + 1

�� add�� $t2, $t2, $t1 # sum = sum + i

�� beq�� $t0, $t1, exit # if i = Northward, go along

�� j�� loop

go out: li�� $v0, iv�� # output msg2

�� la�� $a0, msg2

�� syscall

�� li�� $v0,ane�� # output sum

�� move� $a0, $t2

�� syscall

�� li�� $v0,4�� # output lf

�� la�� $a0, lf

�� syscall

�� li�� $v0,10�� # leave

�� syscall

�� .data

msg1: .asciiz�� "\nNumber of integers (N)?� "

msg2: .asciiz�� "\nSum� =�� "

lf:�� .asciiz�� "\northward"

Output

Number of integers (N)? v

Sum = 15

Comments on the plan

In MIPS, registers accept names likewise as numbers.� Some of the register names that are used in this program are�

Register proper noun	Number	Usage
$v0	two	Expression evaluation and role results
$a0	iv	Argument 1
$t0	8	Temporary (non preserved across call)
$t1	9	Temporary (not preserved across telephone call)
$t2	10	Temporary (non preserved across telephone call)

li $t1, 0 # initialize counter (i)

Temporary register $t1 contains the count.

li $t2, 0 # initialize sum

Temporary annals $t2 contains the sum.

loop: addi $t1, $t1, i # i = i + 1

Increment the counter by one.

add $t2, $t2, $t1 # sum = sum + i

Add the counter to theum.

beq $t0, $t1, exit # if i = N, continue

If the counter equals the number of integers, so leave the loop.

j loop

Else perform the summation again.

exit: li $v0, four # output msg2

Statement to execute upon leaving the loop.

[All contents copyright � 1995 Ronald Northward. Ciminero.� Used with permission.]